There is a continuing trend within the microelectronics industry to incorporate more circuitry having greater complexity on a single integrated circuit (IC) chip. Maintaining this trend generally entails shrinking the size of individual devices within the circuit by reducing the critical dimensions (CDs) of device elements along with the pitch, or the CD of such an element added to the spacing between elements. As used herein, the term “critical dimension(s)” refers to the smallest width or dimension of a line, hole, or space between two lines or two holes that is defined in a predetermined set of design rules for designing an integrated circuit. Microlithography tooling and processing techniques play an important role in resolving the features necessary to fabricate devices and, accordingly, are continually under development to meet industry milestones relating to the CD and pitch characteristics of each new technology generation.
High numerical aperture (NA) 193 nanometer (nm) optical projection stepper/scanner systems in combination with advanced photoresist processes are now capable of routinely resolving complex patterns that include isolated and dense resist features having CDs and pitches, respectively, well below the exposure wavelength. However, to meet the requirements of device design rules, which continue to push the resolution limits of existing processes and tooling, other more specialized techniques have been developed to further enhance resolution. These include double patterning techniques in which device patterns having potentially optically unresolvable features are decomposed into two or more complementary, and more easily resolvable patterns, each containing features with larger CDs and/or a relaxed pitch.
To use double patterning techniques, a target pattern layout, e.g., master pattern layout, must be double patterning compliant. In general, this means that the target pattern layout can be decomposed into two separate patterns that each may be printed in a single layer using existing photolithography tools. A target pattern layout may have many regions or areas that cannot be printed because the features in those areas are spaced too close to one another for existing photolithography tools to be able to print such closely spaced features as individual features. To the extent a target pattern layout has an even number of such regions, such a pattern is sometimes referred to as an “even cycle” pattern, while a target pattern layout that has an odd number of such regions is sometimes referred to as an “odd cycle” pattern. Even cycle patterns can be formed using double patterning techniques, while odd cycle patterns cannot be formed using double patterning techniques. In some target patterns, odd cycles can be removed by applying metal stitching, which is a process for breaking one polygon into two overlapping polygons that are patterned on separate single layers.
An integrated circuit includes a plurality of cells that each comprises a plurality of metal line type features arranged to provide a particular logic function of the circuit. The cells need to be connected by metal lines to generate the integrated circuit, which is often done by EDA tools called Routers. Double patterning technology is commonly used to define the dense metal routing layers in 20 nm and 14 nm technologies. Often, adjacent cells need to be coupled. One approach is to define a back-to-back (B2B) route between border pins (e.g., metal line type features that border their respective cells) of the adjacent cells in the same metal layer, e.g., often the first metal layer, as border pins. The width of the B2B metal route line is often the minimum critical dimension of the metal line width. In double patterning technology, it can happen that the B2B metal route line introduces odd cycles that make the resulted metal layout not decomposable. To maintain the decomposability of the resulted metal routing layer, a metal stitch on the B2B metal connection is often needed. Unfortunately, typical design rules for spacing and end-end stitches require significant space for such B2B routes that are often not compatible with double patterning technology, thereby limiting the decomposability of many target or master pattern layouts into two or more complementary patterns. As such, routing between the various cells becomes more complicated and can lead to routing congestion.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that are compatible with double patterning processes and allow B2B routing in a single layer, e.g., first metal layer, of an integrated circuit. Moreover, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that help reduce routing congestion. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.